The amplification of the input signal is limited by the maximum supply voltage. The input signal can only be amplified to the extent that it can still be linearly amplified. In pipeline analog-to-digital converters (ADCs), this problem is solved by a feedback of the signal. The signal is subsequently evaluated by one or more comparators and this value is subtracted from the input signal of the comparators so that then only the difference, the so-called residual error, is amplified. Pipeline ADCs have to be laboriously calibrated in order to prevent uncontrolled changes in the residual error due to a shift of the operating point. Therefore, pipeline ADCs cannot be switched on and off suddenly since this can lead to a shift of the operating points.
U.S. Pat. Appln. No. 2014/0232577 A1 discloses an analog-to-digital converter comprising a first and a second analog-to-digital conversion cell as well as a control unit. The control unit is configured to generate a control signal that generates a first and a second input range with respect to the same voltage range as well as a first and a second timing element at different phases when a signal that specifies a mode displays a first mode. The control unit is also configured to generate another control signal that generates the first and the second input range with respect to a continuous voltage range as well as a first and second timing element at the same phase when a signal that specifies a mode displays a second mode.
International patent application WO 2004/051858 A2 discloses a method, an apparatus and a system for converting an input voltage into a digital output signal. A comparison to a reference voltage in one or more (flash-type) analog-to-digital converters generates the digital output signal representing the input voltage. If more than one analog-to-digital converter is used, the analog-to-digital converters are linear.